1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to reading-related circuitry in a semiconductor memory device.
2. Description of the Background Art
In recent years, as the storage capacity of semiconductor integrated circuit devices has increased, the critical dimension (the minimum manufacturable size) of transistors which form memory cells in the devices has been reduced as well. This gives rise to the necessity of miniaturizing transistors which form peripheral circuits and interconnections as well as the necessity of miniaturizing those which form memory cells.
The miniaturization of transistors to form sense amplifiers used for sensing slight potential difference generated between a bit line pair at the time of reading out data from a memory cell means a decline in the current driving capability per transistor. Thus, time required for the sense amplifier circuit to driving input/output (hereinafter xe2x80x9cI/Oxe2x80x9d) line pairs in the array to indirect peripheral circuits such as an I/O line pair to a main amplifier increases.
A so-called direct-sense scheme is known as a method for solving such a disadvantage. An example of the direct-sense scheme is shown in FIG. 30.
The gates of transistors 902 and 904 receive the potential levels of data line pairs DL1 and /DL1, respectively, the potential difference of which is amplified by a sense amplifier 900 according to the storage information of a selected memory cell.
The sources of transistors 902 and 904 are supplied with a ground potential through a transistor 906 having its gate potential controlled by read control signal iore.
Transistor 902 has its drain connected to a data line DL2 through a transistor 908 having its gate potential controlled by a reading control signal iore. Meanwhile, transistor 904 has its drain connected to a data line /DL2 through a transistor 910 having its gate potential controlled by reading control signal iore.
Data read out from a memory cell is transmitted to an indirect peripheral circuit 920 by data line pair DL2, /DL2.
Hereinafter, the circuit formed by transistors 902 to 910 will be called xe2x80x9ca sub-amplifierxe2x80x9d.
In such direct sense scheme, data line pair DL1, /DL1 and data line pair DL2, /DL2 are isolated by transistors 902 and 904. As a result, the capacity driven by sense amplifier 900 is simply that of data line pair DL1, /DL1 to transistors 902 and 904, while data line pair DL2, /DL2 are driven by the sub-amplifier.
More specifically, the capacity driven by sense amplifier 900 is restrained, which allows for accessing at a higher speed.
However, in order to further increase the accessing speed, the following problem will be encountered.
In the conventional configuration shown in FIG. 30, a sense amplifier itself is often provided at the position of the sub-amplifier described above.
Alternatively, such a sub-amplifier is often located at a crossing point of a sense amplifier band and a sub-word driver band (hereinafter referred to as xe2x80x9ca cross pointxe2x80x9d).
FIG. 31 is a schematic block diagram of an example of such a configuration.
Referring to FIG. 31, there are provided a main row decoder 940 and a column decoder 950 corresponding to a memory mat 930.
Memory mat 930 is divided into sub-blocks 936 by sense amplifier bands 932 and word driver regions 934.
In this configuration, sub-amplifiers SUA are provided at cross points of local I/O line pairs in the row-direction and global I/O line pairs in the column direction.
Signal iore to control sub-amplifier SUA is generated by main row decoder 940 and transmitted in the row-direction to sub-amplifier SUA.
However, the data reading operation itself is the operation by the column-related circuitry, and therefore, a signal line to transmit signal iore provided in the row-direction and a column selecting line YS to transmit a column selecting signal are perpendicular to each other. When column selecting line YS and the path to transmit signal iore are provided perpendicular to each other, a timing margin should be secured between the signals in view of skew between the signals, which impairs the accessing time from being reduced.
The miniaturization of a transistor forming sub-amplifier SUA increases sub-threshold leakage current by the transistor, and the power consumption disadvantageously increases by a constant amount of leakage current generated, even if the circuit is in a stand-by state, in other words, if transistor 906 is in a disconnected state.
It is an object of the present invention to provide a semiconductor memory device which permits accessing time to be improved in a large scale integrated semiconductor memory device.
Another object of the present invention is to provide a synchronous semiconductor memory device which permits the power consumption in a stand-by state to be reduced.
Briefly stated, a semiconductor memory device according to the present invention includes a memory cell array, a row selecting circuit, a column selecting circuit, a plurality of sense amplifiers, a plurality of sub-I/O line pairs, a selecting gate circuit, a main I/O line pair, and a plurality of sub-amplifiers.
The memory cell array includes a plurality of memory cells arranged in a matrix of rows and columns. The memory cell array includes a plurality of memory cell blocks. The row selecting circuit selects a corresponding memory cell row in response to an address signal. The column selecting circuit selects a corresponding memory cell column in response to an address signal.
The plurality of sense amplifiers are provided corresponding to memory cell columns in each memory cell block to amplify data from a selected memory cell.
The plurality of sub-I/O line pairs are provided corresponding to the plurality of memory cell blocks. The selecting gate circuit transmits reading data from a sense amplifier corresponding to a selected memory cell column in response to a column selecting signal transmitted in the memory cell column direction from the column selecting circuit. The main I/O line pair is provided in common to the plurality of memory cell blocks.
The plurality of sub-amplifiers transmit reading data transmitted from a sub-I/O line pair to the main I/O line pair. Each sub-amplifier includes first and second MOS transistors which each receive the potential of a sub-I/O line for a corresponding gate and discharge the corresponding main I/O line pair from a second potential to a first potential, an activation circuit which responds to a row-related control signal transmitted in the row direction of the memory cells and a column-related control signal transmitted in the column direction of the memory cells to activate the first and second transistors to perform discharging operation.
A semiconductor memory device according to another aspect of the present invention includes a memory cell array, a plurality of sense amplifiers, a plurality of I/O line pairs, a plurality of precharge circuits, a plurality of sub-amplifiers, and a segment signal line.
The memory cell array includes a plurality of memory cells arranged in a matrix of rows and columns. The memory cell array is divided into a plurality of memory cell blocks arranged in a matrix of rows and columns.
The plurality of sense amplifiers are provided corresponding to memory cell columns in each memory cell block to amplify data from a selected memory cell as complementary signals.
Each of the I/O line pairs is provided in common to at least two of memory cell blocks. The precharge circuits precharge I/O line pairs to a first potential. The plurality of sub-amplifiers are provided corresponding to the sense amplifiers to transmit read data to the I/O line pairs. Each of the sub-amplifiers includes first and second MOS transistors which have gates to receive complementary signals from a sense amplifier corresponding to said selected memory cell and discharge a corresponding one line of I/O line pair from the first potential to a second potential.
The segment signal lines supply the second potential to the first and second transistors.
A semiconductor memory device according to another aspect of the present invention includes a first plurality of banks, a row selecting circuit, a column selecting circuit, a plurality of first column selecting lines, a plurality of first I/O line pairs, and a first selecting circuit.
The first plurality of banks are arranged in the column-direction. The banks each include a second plurality of memory cell blocks arranged in the row-direction. The memory cell blocks each include a plurality of memory cells arranged in a matrix of rows and columns and bit line pairs provided corresponding to memory cell columns.
The row selecting circuit responds to an address signal to select a corresponding bank and a corresponding memory cell row. The column selecting circuit generates a column selecting signal to select a memory cell corresponding column in response to an address signal.
The plurality of the first column selecting lines are provided in common to the first plurality of banks in the column direction and transmit a column selecting signal.
The plurality of first I/O line pairs are provided corresponding to the first plurality of banks in the row-direction. The first selecting circuit transmits reading data from a memory cell column selected in response to a column selecting signal to the first I/O line pair.
The first selecting circuits are provided corresponding to memory cell columns in a memory cell block and include a plurality of first gate circuits controlled by a corresponding first column selecting line of the first column selecting lines. Each of the first gate circuits includes a first transfer gate circuit provided on a transmission path between a bit line pair for a corresponding memory cell column and one of the first I/O line pairs and controlled by a corresponding first column selecting line to attain a conductive state or a disconnected state, and a direct sense type gate circuit provided in series with the first transfer gate circuit on the transmission path.
A semiconductor memory device according to yet another aspect of the present invention includes a first plurality of banks, a row selecting circuit, a plurality of bank selecting lines, a column selecting circuit, a plurality of column selecting lines, a plurality of I/O line pairs, and a plurality of selecting circuits.
The first plurality of banks are provided in the column-direction. Each of the banks includes a second plurality of memory cell blocks provided in the row-direction. Each of the memory cell blocks includes a plurality of memory cells arranged in a matrix of rows and columns and bit line pairs provided corresponding to memory cell columns.
The row selecting circuit responds to an address signal to generate a bank selecting signal for selecting a corresponding bank and selects a corresponding memory cell row. The plurality of bank selecting lines are provided in the row-direction for each of the banks to transmit a bank selecting signal. The column selecting circuit responds to an address signal to generate a column selecting signal for selecting a corresponding memory cell column. The plurality of column selecting lines are provided in common to the first plurality of banks in the column-direction to transmit a column selecting signal. The plurality of I/O line pairs are provided in the row-direction corresponding to the first plurality of banks.
The selecting circuits transmit read data from a selected memory cell column in response to a column selecting signal. The selecting circuits each include a plurality of gate circuits provided corresponding to the memory blocks and controlled by a corresponding column selecting line. The gate circuits each include a product signal generating circuit which responds to an activation of a corresponding column selecting line and an activation of a corresponding bank selecting line to generate an active driving signal, and a transfer gate circuit provided on the transmission path between a bit line pair for a corresponding memory cell column and one of the I/O line pairs and controlled by a driving signal to attain a conductive state or a disconnected state.
Therefore, a main advantage of the present invention resides in that the timing between signals can be readily controlled for small skew between the signals in connection with the control of a sub-amplifier and the control for column selection, which allows for high speed accessing.
Another advantage of the present invention resides in that only a memory cell block to which a selected memory cell belongs can be selectively operated, and therefore the power consumption and noise can be reduced.
Yet another advantage of the present invention resides in that high speed operation can be implemented while restraining increase in the layout area in a horizontally divided bank arrangement.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.